In modern information processing systems an important consideration is the interface between a plurality of I/O devices, such as mass storage devices and telecommunications peripherals, and the system main memory. The main memory may be coupled to a high speed, high performance central system data and address bus. The system bus is typically also coupled to other high speed system units, or bus connections, such as one or more central processing units (CPUs) and cache memory systems associated with the CPUs. Thus, a problem is created in that the I/O devices typically source or sink data at least an order of magnitude more slowly than these high speed bus connections. In order to achieve a maximum system bus bandwidth the interface between the I/O devices and the main memory or other system bus connections is therefore preferably not a direct interface. That is, the I/O devices are preferably not directly coupled to the system bus but are provided with an IO BUS which, is especially adapted for I/O-type data transfers. It can be appreciated that in a system having such an IO BUS that a bus connection which bidirectionally couples the IO BUS to the system bus is required to accommodate the differences in speed and other operating characteristics between the two buses.
One operating characteristic which may exist between the two buses may relate to differences in bus voltage potentials. For example, if the high speed system bus were implemented with emitter coupled logic (ECL) devices while the IO BUS was implemented with transistor-transistor logic (TTL), or equivalent, devices the differences between bus operating voltages makes a direct interconnection between the ECL bus and the TTL bus impossible to achieve.
Furthermore, if the bus connection which couples the IO BUS to the system bus has storage for buffering data, or information units, which pass between the system bus and the IO BUS then it is known to provide the IO BUS with a signal line for informing the IO Processors when the storage is full. Inasmuch as the storage preferably provides both read and write buffers it can be appreciated that it would be desirable to differentiate between a condition wherein only the read buffer is full and not the write buffer, and vice versa. Thus, IO Processors which desire to write data to the system bus are not inhibited from writing data during a time when only the read buffer is full. Conversely, IO Processors which desire to read data from the system bus are not inhibited during a time when only the write buffer is full.